The present invention relates to a power supply circuit and a semiconductor memory device having such a power supply circuit, and more particularly to a single-source type power supply circuit including a booster circuit and a non-volatile semiconductor memory device having such a power supply circuit.
FIG. 1 is a schematic circuit diagram of a typical booster circuit to be used for a power supply circuit.
The booster circuit includes diodes D1 through D6, capacitors C1 through C5 and capacitor Ca, and inverters G1, G2.
The anode of the diode D1 is supplied with external supply voltage Vcc. The cathodes of the diodes D1 through D5 are respectively connected to the anodes of the diodes D2 through D6 and the anodes of the diodes D2 through D6 are also connected to the first terminals of the capacitors C1 through C5 respectively. The other ends of the capacitors C1, C3 and C5 are connected to the output terminal of inverter G1 whose input terminal is fed with clock signal OSC generated by an oscillator. The input terminal of the inverter G1 operates as the signal input terminal of the booster circuit. The other ends of the capacitors C2 and C4 are fed with clock signal OSC. The cathode of the diode D6 outputs voltage Vccint. A stabilizing capacitor Ca is connected between the cathode of the diode D6 and ground.
Electric charges are transferred from diode to diode in an alternating manner in the booster circuit in accordance with clock signal OSC fed from an oscillator. As a result, it generates voltage Vccint that is higher than external supply voltage Vcc.
FIG. 2 is a schematic circuit diagram of a typical oscillator to be used for a power supply circuit.
The first input terminal of NAND-gate 1 is fed with signal CPE for enabling the booster circuit. The output terminal of the NAND-gate 1 is connected to, for example, a 4-stage inverter 2 including four serially connected inverters. The output signal of the 4-stage inverter 2 is fed to the second input terminal of the NAND-gate 1. For example, an inverted signal of the output signal of the inverter 2 is used as clock signal OSC.
When signal CPE rises to a high level, the oscillator outputs a clock signal OSC that alternately rises to a high level and falls to a low level. When signal CPE goes to a low level, the oscillator stops oscillating and outputs a low level signal.
FIG. 3 is a circuit diagram of a known power supply circuit including a booster circuit as shown in FIG. 1 and an oscillator as shown in FIG. 2. The power supply circuit provides a booster circuit system typically used for a non-volatile semiconductor memory device.
The oscillator 12 and the booster circuit 13 have respective circuit configurations identical with those illustrated in FIGS. 2 and 1. The output voltage Vccint of the booster circuit 13 is divided by resistor 17 and supplied to the inverted input terminal of a differential amplifier 11. The non-inverted input terminal of the differential amplifier 11 is supplied with reference voltage Vref. The differential amplifier 11 supplies signal CPE to the oscillator 12.
The differential amplifier 11 compares the reference Voltage Vref and the voltage obtained by regulating the voltage Vccint and turns on/off the booster circuit 13 in accordance with the outcome of the comparison. In this way, the output voltage (boosted voltage) Vccint of the booster circuit 13 is held to a desired level that may be, for example, equal to 10V.
As shown in FIG. 3, the output voltage Vccint of the booster circuit 13 is supplied to regulator circuit 14 and Y-selector 16.
For example, the regulator circuit 14 may generate a voltage of 6.5V in the write (program) verify mode of operation, and a voltage of 10V which is equal to the output voltage Vccint in the write (program) mode. Likewise, it may generate a voltage of 2.5V in the erase mode, and a voltage of 3.5V in the erase verify mode.
The output voltage Vout of the regulator circuit 14 is supplied to row decoder 15. The row decoder 15 selects a word line of a memory cell array (not shown) in accordance with a row select signal.
The Y-selector 16 selects a bit line of the memory cell array (not shown) in accordance with a column select signal.
The output voltage Vccint of the booster circuit 13 is subjected to a variety of loads.
Firstly, the capacitance of the Y-selector 16 itself provides a load.
Additionally, in the write (program) mode, the regulator circuit 14 directly applies the obtained voltage Vccint to the row decoder 15. Accordingly, the capacitance 18 of the word line (which is selected by the row decoder 15 and to which the output voltage Vccint of the booster circuit 13 is directly supplied) makes a load for the voltage output terminal of the booster circuit 13. On the other hand, in the erase mode, the write verify mode or the erase verify mode, the output voltage Vccint of the booster circuit 13 is shifted to a lower voltage by the regulator circuit 14 and, therefore, the capacitance 18 of the word line does not make any load. Therefore, the load to be added to the voltage Vccint varies depending on the mode of operation.
FIGS. 4A and 4B show operating waveforms of the power supply circuit, or waveforms of the output voltage Vccint that may appear when the booster circuit 13 of the power supply circuit in FIG. 3 starts operating and the output voltage Vccint rises from 0V to 10V.
FIG. 4A shows a waveform of the output voltage Vccint that may be observed when there is a heavy load typically in the write (program) mode, whereas FIG. 4B shows a waveform of the output voltage Vccint that may appear when there is only a light load typically in the erase mode.
In the case of a light load as shown in FIG. 4B, the voltage Vccint overshoots to show a zig-zag waveform because of the light load and makes it difficult to output a well controlled stable voltage Vccint. When an overshot voltage Vccint is supplied from the power supply circuit to a device the circuit drives, it may exceed the withstand voltage level of the device and hence can degrade the performance of the device and damage its reliability.
In view of these problems, therefore, it is highly desirable to reduce the fluctuations in the output voltage of a power supply circuit that appear when a light load is applied to the voltage output terminal of the booster circuit and make it possible to provide a well controlled voltage from the booster circuit. Thus, there is a strong demand for a power supply circuit that can improve the reliability of any device it drives and also for a semiconductor memory device having such a power supply circuit.
Meanwhile, known non-volatile semiconductor memory devices include flash EEPROMs. A flash EEPROM includes stacked transistors having a floating gate and a control gate as memory cells. Such a memory cell changes its threshold voltage for data writing/erasing operations as electrons are charged into and discharged from it through the floating gate.
Flash memories adapted to be charged with hot electrons for data writing are currently driven either by a two-source type power supply circuit that uses a power supply of Vcc=5V for data writing and another power supply of Vpp=12V for data erasing, or by a single-source type power supply circuit that uses only a power supply of Vcc=5V. When a single-source type power supply circuit is used, power supply voltage Vpp for data erasing is obtained by means of a booster circuit.
The trend in recent years is in favor of power saving low voltage power supply circuits and 3V is typically used as power supply voltage. From the viewpoint of convenience, a single-source type power supply circuit may be superior to a two-source type power supply circuit.
Now, when the power supply voltage of a known power supply circuit adapted to supply the voltage directly to the control gate in the read mode is reduced from 5V to 3V, then the voltage supplied to the control gate also falls to 3V, resulting in reduction of the current flowing to the memory cells. A reduced cell current gives rise to a reduced reading speed and a reduced margin relative to the power supply voltage. In other words, with such a circuit, the voltage for data reading and the voltage for data writing and erasing have to be generated internally.
However, when a power supply voltage is used, a plurality of booster circuits may have to be employed to generate a voltage required within the chip and a number of different voltage levels have to be selectively used by means of a switching circuit to provide voltages necessary for reading, writing and erasing data respectively. Then, such a switching circuit is required to supply the generated voltage to the destination such as a control gate of memory cells without lowering it. Known control circuits of the type under consideration typically include depletion type transistors to prevent the generated voltage from falling by the threshold voltage of the transistors. However, the use of depletion type transistors is accompanied by a problem of an increased number of manufacturing steps and a high chip cost.
In view of the above circumstances, there is a strong demand for a power supply circuit that can provide any desired voltage from its booster circuit to reduce the chip cost and also for a semiconductor memory device having such a power supply circuit.
Accordingly, it is an object of the present invention to provide a power supply circuit adapted to supply a desired voltage from its booster circuits in a highly controlled manner by reducing fluctuations in the output voltage that can appear when a light load is applied to the voltage output terminal of its booster circuits in order to improve the reliability of the device driven by the circuit and also a semiconductor memory device having such a power supply circuit.
It is another object of the present invention to provide a power supply circuit adapted to supply a desired voltage from its booster circuits 13 without using costly transistors in order to reduce the chip cost and also a semiconductor memory device having such a power supply circuit.
According to one aspect of the present invention, there is provided a power supply circuit comprising: a plurality of booster circuits, each being adapted to generate a boosted voltage in accordance with a clock signal and supply it to a common voltage output terminal; and a control circuit for selecting a number of booster circuits to be operated out of the plurality of booster circuits in accordance with a level of the boosted voltage to be provided at the common voltage output terminal.
According to another aspect of the present invention, there is provided a non-volatile semiconductor memory device comprising: a memory cell array having a plurality of non-volatile memory cells; and a power supply circuit for preparing a predetermined boosted voltage to be used for generating at least one of various voltages supplied to the non-volatile memory cells in write and erase modes, the power supply circuit including: a plurality of booster circuits, each being adapted to generate the boosted voltage in accordance with a clock signal and supply it to a common voltage output terminal, and a control circuit for selecting a number of booster circuits to be operated out of the plurality of booster circuits in accordance with a level of the boosted voltage to be provided at the common voltage output terminal.
According to another aspect of the present invention, there is provided a non-volatile semiconductor memory device comprising: a memory cell array having a plurality of non-volatile memory cells; a write/erase circuit for the plurality of non-volatile memory cells; and a circuit for generating desired voltages which are different from an external power supply voltage and applied to the plurality of non-volatile memory cells, the circuit including a booster circuit for generating a boosted voltage, wherein a power of the booster circuit is set higher in a write mode and is set lower in an erase mode when the boosted voltage of the booster circuit falls below a predetermined voltage.
According to a further aspect of the present invention, there is provided a semiconductor memory device comprising: a first booster circuit having first and second output terminals, for outputting a first voltage obtained by boosting a power supply voltage from the first and second output terminals; and a second booster circuit having an output terminal connected to the second output terminal of the first booster circuit, for outputting a second voltage higher than the first voltage by boosting the power supply voltage, the first voltage being supplied to the output terminal of the second booster circuit even when the second booster circuit stops its voltage boosting operation.
According to another aspect of the present invention, there is provided a semiconductor memory device comprising: a first booster circuit for outputting a first boosted voltage obtained by boosting a power supply voltage; a second booster circuit for outputting a second boosted voltage higher than the first boosted voltage by boosting the power supply voltage; a regulator circuit for regulating the second boosted voltage output from the second booster circuit to generate a regulated voltage; a transistor having a current path with an end applied with a voltage from the first booster circuit in a write or erase mode and the other end connected to an end of a current path of a memory cell; and a circuit for shifting a level of a signal to a gate of the transistor supplied to a level of the regulated voltage output from the regulator circuit.
Additional objects and advantages of the present invention will be set forth in the description which follows, and in part will be obvious from the description, or may be learned by practice of the present invention. The objects and advantages of the present invention may be realized and obtained by means of the instrumentalities and combinations particularly pointed out in the appended claims.